The present invention relates to a static random access memory (“SRAM” hereinafter) and a semiconductor device.
By virtue of the progress of microfabrication technology, the operation speed and the integration degree of LSIs (Large Scale Integrated Circuits) have been increasing in recent years. In order to put an LSI that operates at high speed into practical use, the reduction in consumption of power of the LSI is one of important technical requirements. That is, generally, the consumption of power increases when an LSI is operated at high speed. Therefore, in order to stably operate the LSI, a ceramic package and radiator fins and so on are needed, resulting in an increased cost. In recent years portable devices have been advancing toward further reduction in size and weight, and the reduction in consumption of power is important also in achieving the long-time use of the devices on batteries as well.
Conventionally, an SRAM cell constructed of four N-type MOS (Metal-Oxide Semiconductor) transistors and two P-type MOS transistors has generally been used. FIG. 9 shows a circuit diagram of a conventional SRAM cell constructed of four N-type MOS (“NMOS” hereinafter) transistors and two P-type. MOS (“PMOS” hereinafter) transistors. FIG. 10 shows the layout of the whole SRAM that employs the SRAM cells having the above construction.
Referring to FIG. 10, the SRAM 1 is constructed roughly of an input/output interface section 2, a memory section 3 through which the SRAM cells are spread, an address decoder section 4 and a data write/read control section 5. The SRAM cells that constitute the memory section 3 have the construction shown in FIG. 9. That is, a bit line B is connected to the source (drain) of a first NMOS transistor 11. A word line WL is connected to the gates of the first NMOS transistor 11 and a second NMOS transistor 12. An inverted bit line BX is connected to the source (drain) of the second NMOS transistor 12.
A drain (source) Y that belongs to the first NMOS transistor 11 and is not connected to the bit line B is connected to the gates of a third NMOS transistor 13 and a first PMOS transistor 15 and further connected to the drains of a fourth NMOS transistor 14 and a second PMOS transistor 16.
A drain (source) XY that belongs to the second NMOS transistor 12 and is not connected to the inverted bit line BX is connected to the gates of the fourth NMOS transistor 14 and the second PMOS transistor 16 and further connected to the drains of the third NMOS transistor 13 and the first PMOS transistor 15.
The sources of the third NMOS transistor 13 and the fourth NMOS transistor 14 are connected to GND, while the sources of the first PMOS transistor 15 and the second PMOS transistor 16 are connected to VDD.
In the above arrangement, semiconductor regions in which a channel is formed when each of the first NMOS transistor 11 through fourth NMOS transistor 14 is turned on are connected to GND. On the other hand, other semiconductor regions in which a channel is formed when each of the first PMOS transistor 15 and the second PMOS transistor 16 is turned on are connected to VDD.
However, the above conventional SRAM has the following problems. That is, in accomplishing a reduced power consumption of the SRAM, a great effect can be obtained by lowering the operating voltage (VDD). However, if the voltage VDD is lowered, then the driving current of the MOS transistors becomes so small that delay time of the circuit disadvantageously increases, resulting in the reduction of the operating speed. As a solution to this problem, it is conceivable to reduce the threshold voltage (Vth) of each MOS transistor such that the driving current of the MOS transistor is not reduced much even with a low voltage. However, if the threshold voltage Vth is reduced, then a leak current of the MOS transistor increases, and this leads to the problem that the power consumption increases great due to the existence of the leak current even in a standby mode.